I guess the current crop of (hi end - what's hi end in a Pee Cee) PeeCees have a bus speed of 800Mhz, and while all that isn't going to the processor for fetching instructions and data, if a quarter of it is, even the dumbest Celeron will think it's quick.
So what to do when Motorola is giving you a bus speed of 167Mhz? Easy, reduce the load on the system bus. Rather than always hitting the system bus for data or instructions, fill up a backside cache with one or two MBs of data or instruction and have it on a bus by itself that runs at 1/2 the processor speed. That way there's always data for the processor and the processor doesn't have to wait for any bus contention between the itself and other system components. The system is quick!
Johnny G4 is right as the high bus speeds negate any advantage an L3 ( 1/4 bus speed ) could offer so caching instructions at that level does nothing even if the pipelines are short.
BUT - the L2s running at 1/2 clock speed are significant speed boosters and the move has been to 512k versions instead of 256 and along with improved pipeline architecture is squeezing more processing speed out as more instructions actually get executed and that's what it's about - clock increases without accompanying pipeline and caching improvements can at times go retrograde. But it's expensive memory to run that high and there are limits to the gains but they are there so current thinking runs to 512k on chip.
Oh a couple more things
RISC chips are smaller cooler and CHEAPER so adding expensive and hot running L2 cache memory is not so costly for the PowerPC crowd as for the CISC crowd - It's an alternative approach allowing slower bus architecture to compete.....to a degree.
Rick you would be correct on L2 only if the bus speeds were approaching 2:1 and the pipelines were very short