Actually, the real reason there is no L3 cache is because the FSB is so fast that the actual memory in a G5 is the equivalent of a G4 L3 cache. L3 cache isn't needed when you can access memory over a fast FSB. The L3 cache in the G4 was making up for the G4's slow FSB.
Edit: and maybe the L3 cache in the G4 was also making up for the small G4 L2 cache. Until the last revision of the G4, the G4 had a small L2 cache.